With over a decade in the valley, Reinfold Physical Innovation Labs has been instrumental in working with customers covering the entire silicon design cycle from design, verification to physical design. Our unique design policy provides you with a round-the-clock development environment by utilizing a combination of onsite and offshore teams.
Behavioral & RTL modeling and test bench development from specification.
Automated test bench development and regression suite generation in C/C++, Specman Elite, Perl and Shell scripts to create. logic and timing verification environment.
Design-for-test strategies, BIST, scan, embedded processor and analog test insertion.
Formal verification, Protocol monitor and checkers, Verilog, C/C++, PLI and Specman based verification, Functional coverage and Code coverage
Logic and test synthesis - Extracted delays, Design-for-Test and test program development.
Integration of event/ cycle accurate simulation, In-circuit emulation and static/ dynamic timing tools for functional and timing verification at different stages of a top down design methodology.
Fault simulation and methodologies for fault grading and test vector generation of partial/ full boundary scan designs.
- Functional Specs
- Design Partitioning
- RTL Design & Simulation
- Functional Verification
- Synthesis for area & Timing Optimization
- Gate level simulation/Formal Verification